The present invention relates to a clock control circuit for controlling a clock such as a data strobe signal, and a data alignment circuit including the same; and, more particularly, to a clock control circuit capable of preventing overlap between a rising strobe signal and a falling strobe signal, and a data alignment circuit including the same.
A semiconductor memory device has been continuously developed to increase integration density and improve an operating speed thereof. To improve the operating speed, a synchronous semiconductor memory device has emerged, which is operable in synchronization with an external clock.
A single data rate (SDR) synchronous semiconductor memory device which inputs or outputs one data via one data pin in synchronization with a rising edge of an external clock during one clock cycle has been proposed and developed. However, the SDR synchronous semiconductor memory device is insufficient to satisfy the speed requirement of a high-speed system. Thus, a double data rate (DDR) synchronous semiconductor memory device was proposed which processes two data during one clock cycle.
In the DDR synchronous semiconductor memory device, two data are consecutively input or output through data input/output pins in synchronization with rising and falling edges of the external clock. The DDR synchronous semiconductor memory device can realize at least two times the bandwidth of the SDR synchronous semiconductor memory device without increasing the frequency of the clock, thus obtaining the high-speed operation.
Because the DDR synchronous semiconductor memory device must output or receive two data during one clock cycle, a data access method employed in the conventional synchronous semiconductor memory device can no longer be used.
If the clock period is about 10 ns, two consecutive data must be processed substantially within about 6 ns, except for the rising and falling time, e.g., about 2 ns (=0.5×4) and time required for meeting other specifications. However, it is difficult for the semiconductor memory device to process two data within that time. Therefore, the semiconductor memory device operates in synchronization with the rising and falling edges of the clock only when receiving/outputting data from/to an external circuit. Substantially, inside the semiconductor memory device, the two data are processed in parallel in synchronization with one edge of the clock.
Thus, a new data access method is necessary in order for a semiconductor memory device to transfer received data to an inner core region or to output data from the core region to an external circuit.
Consequently, a data input buffer of the DDR synchronous semiconductor memory device prefetches 2-bit data in synchronization with rising and falling edges of the clock, and then, transfers the prefetched data to an inner core region as even-bit data or odd-bit data in synchronization with a rising edge of a main clock.
As a semiconductor device such as a central processing unit (CPU) operates at a higher speed, semiconductor memory devices are required to also operate at a higher speed. To meet this requirement, a data alignment circuit is being used. The data alignment circuit prefetches 4-bit data in the case of a DDR2 synchronous semiconductor memory device or 8-bit data in the case of a DDR3 synchronous semiconductor memory device, and transfers the data to an internal region of the semiconductor memory device.
Meanwhile, in order to implement accurate timing in data input/output, a data strobe signal DQS for noting data transfer are input to the semiconductor memory device with a corresponding data from an external device such as a CPU or a memory controller.
FIG. 1 is a block diagram of a data alignment circuit used in a conventional semiconductor memory device.
Referring to FIG. 1, a data alignment circuit 110 performs 8-bit prefetch. The data alignment circuit 110 receives data DIN and data strobe signals DQS and DQSB via buffers 101, 102 and 103. The data DIN are input in series, and the data alignment circuit 110 aligns the data DIN in parallel W0 to W7 by using data strobe signals DQS and DQSB. As shown, the data alignment circuit 110 includes D flip-flops 111, 113, 118, 119, 120 and 121 and D-latches 112, 114, 115, 116 and 117.
A data input buffer 101 buffers the data DIN, and compares a voltage level of the data DIN with a voltage level of a reference voltage (VREF) to determine whether the data DIN is a logic high data or a logic low data.
A strobe buffers 102 and 103 receive a data strobe signal DQS and a data strobe bar signal DQSB, but through opposite input terminals to each other. Then, the strobe buffer 102 outputs a rising strobe signal DQSR that is enabled during a high level duration of the data strobe signal DQS. The strobe buffer 103 outputs a falling strobe signal DQSF that is enabled during a low level duration of the data strobe signal DQS.
The D flip-flops 111 and 113 and the D-latches 112, 114, 115, 116 and 117 in the data alignment circuit 110 align the serial data in parallel W0 to W7 by using the rising strobe signal DQSR and the falling strobe signal DQSF. The data W0 to W7 aligned in parallel are written to global input/output (I/O) lines GIO_00 to GIO_07 by I/O sense amplifiers 131 to 138.
FIG. 2 is a timing view illustrating an operation of the data alignment circuit 110. The operation of the data alignment circuit will now be described with reference to FIGS. 1 and 2.
In a write operation of 8-bit prefetch, eight serial data D0 to D7 are aligned in parallel, thereby simultaneously writing the eight data D0 to D7 at a clock next to the input of the last data bit D7.
The data D0, D2, D4 and D6 centered on the rising edge of a data strobe signal DQS are aligned using a rising strobe signal DQSR. Hereinafter, the data D0, D2, D4 and D6 are referred to as rising data. The data D1, D3, D5 and D7 centered on the falling edge of the data strobe signal DQS are aligned using a falling strobe signal DQSF. Hereinafter, the data D1, D3, D5 and D7 are referred to as falling data. The process of aligning the rising data D0, D2, D4 and D6 input at the rising edge and the process of aligning the falling data D1, D3, D5 and D7 input at the falling edge are independently performed in the same basic operating manner. Thus, for explanation of the operation of the data alignment circuit, the process of aligning the rising data D0, D2, D4 and D6 will be described.
First, data DIN are input in series to the D flip-flop 111 via the data input buffer 101. The rising data D0 of the data DIN is applied on an R0 line at the rising edge of the rising strobe signal DQSR. When the falling strobe signal DQSF is ‘HIGH’, the data D0 on the R0 line is applied on a W6 line by the D-latch 112. Then, the data D0 on the W6 line is shifted by half the clock cycle to be applied on an R1 line by the D-latch 114, and shifted again by half the clock cycle to be applied on a W4 line by the D-latch 116. Meanwhile, a signal DCLK_BL8 including burst length information is enabled after two clocks since the data input point. The data D0 on the W4 line is applied on a W0 line by the D flip-flop 119 by using the DCLK_BL8 signal. The rising data D2 is applied on the R0 line at the rising edge of the rising strobe signal DQSR. When the falling strobe signal DQSF is ‘HIGH’, the data D2 on the R0 line is latched and applied on the W6 line by the D-latch 112. Thereafter, the data D2 on the W6 line is latched and applied on a W2 line by the D flip-flop 118 by using the DCLK_BL8 signal. The rising data D4 is applied on the R0 line at the rising edge of the rising strobe signal DQSR. When the falling strobe signal DQSF is ‘HIGH’, the data D4 on the R0 line is latched and applied on the W6 line by the D-latch 112. Then, the data D4 on the W6 line is shifted by half the clock cycle to be applied on the R1 line by the D-latch 114 and shifted again by half the clock cycle to be applied on the W4 line by the D-latch 116. The rising data D6 is applied on the R0 line at the rising edge of the rising strobe signal DQSR. When the falling strobe signal DQSF is ‘HIGH’, the data D6 on the R0 line is latched and applied on the W6 line by the D-latch 112. In such a manner, the D0, D2, D4 and D6 are respectively applied on the W0, W2, W4 and W6 lines. Thereafter, the data D0, D2, D4 and D6 on the W0, W2, W4 and W6 are simultaneously written to the global I/O lines GIO-00, GIO-02, GIO_04 and GIO_06 by a signal DINSTBP that is enabled after four clocks since the data input point, respectively.
The data D1, D3, D5 and D7 input, centered on the respective falling edges of the data strobe signal DQS are aligned in the same manner as that of aligning the data D0, D2, D4 and D6 centered on the rising edges. This is illustrated in FIG. 2 in detail, and the detailed description thereof will be omitted.
FIG. 3 is a circuit diagram of a D-latch illustrated in FIG. 1. Referring to FIG. 3, the D-latch includes a pass gate and an inverter latch. It can be seen from FIG. 3 that when a signal being input to a clock terminal CLK is ‘HIGH’, the D-latch latches data input to an input terminal IN. The signal being input to the clock terminal CLK is a rising strobe signal DQSR or a falling strobe signal DQSF according to the D-latch.
The rising strobe signal DQSR and the falling strobe signal DQSF each have a pulse width corresponding to half the clock cycle, i.e., ½×tCK. However, the pulse widths of the rising strobe signal DQSR and the falling strobe signal DQSF may increase as the signals pass through a gate or because of a variety of factors of a circuit. In this case, the D-lath including the pass gate and the inverter latch cannot accurately shift data.
FIG. 4 is a timing diagram for explaining a limitation caused by an increase in pulse width of a rising strobe signal DQSR and a falling strobe signal DQSF.
Referring to FIG. 4, a pulse of the rising strobe signal DQSR overlaps a pulse of the falling strobe signal DQSF, causing the D-lath to fail to accurately shift data. Finally, the data are misaligned with respect to the terminals W1 to W7.
The data must be aligned as follows: D0=W0, D1=W1, D2=W2, D3=W3, D4=W4, D5=W5, D6=W6, and D7=W7. However, as shown in FIG. 4, the data are misaligned as D6=W4, D2=W0 and D3=W1. Consequently, data cannot be accurately written to a semiconductor memory device, causing a fail in a write operation of the semiconductor memory device.